Emitter-coupled logic (ECL) circuits require a reference voltage which is used to set the amount of current going through each of the ECL gates. One reference voltage source is used to supply a reference voltage for numerous ECL circuits. Typically, this scheme works well except when the voltage drops along the power supply lines of the circuit cause the reference voltage to become invalid. The voltage drops are manifested by voltage drops along the lower-voltage power supply rail due to series resistance along the path between the reference voltage source and a particular ECL circuit. Another problem with conventional ECL gates is their need for a supply voltage of a large magnitude. Consequently, conventional ECL circuits are not well suited for use with the ever decreasing power supply voltages associated with tomorrow's circuits, particularly, 3.3 volts and below. ECL circuits which provide a reference voltage source local to each ECL circuit solves the above problem. A local reference voltage circuit is provided for each ECL circuit of a plurality of ECL circuits. In addition, CMOS logic can be used to provide for a low power standby mode when the ECL gates are not in use. A need exists to provide an ECL circuit with improved operating characteristics which additionally possesses a low power standby mode.
FIG. 1a illustrates a schematic drawing of prior art ECL circuit 1 implementing a logic OR gate. Local reference sub-circuit 3 provides a local reference voltage for ECL circuit 1 as well as provides enabling of circuit 1 through circuit enable input EN. Local reference sub-circuit 3 further comprises first inverter 9 and second inverter 10. First inverter 9 includes p-channel field effect transistor 2 and n-channel field effect transistor 4. Second inverter 10 includes p-channel field effect transistor 11 and n-channel field effect transistor 6. For low power output applications, transistor 11 typically has a gate width of 60 microns (.mu.m). For high performance applications (greater power), the gate width of transistor 11 is on the order of 180 .mu.m. A logic high enable signal at enable input EN enables local reference sub-circuit 3 as well as the remainder of circuit 1. Within sub-circuit 3, the local reference voltage for the circuit 1 is measured from the base of n-type bipolar transistor 8, connected to and between resistors 5 and 7, and circuit ground. For low power output applications, transistor 8 typically has an emitter area substantially equal to 1.2 .mu.m.sup.2 and transistor 8 is fabricated as a single-sided base transistor. The value of the local reference current (which is output from local reference sub-circuit 3 at output REF) generated by local reference sub-circuit 3 is determined substantially by the emitter and collector currents through transistor 8 which are primarily determined by the voltage drop across resistor 5. To ensure that the emitter and collector currents through transistor 8 are primarily determined by the voltage drop across resistor 5, the gate width of transistor 6 is made as wide as possible. This prevents transistor 6 from playing a major role in setting the current level of the current through the emitter and collector of transistor 8. The inverter formed by transistor 2 and transistor 8 ensures that the trip point of local reference sub-circuit 3 is midway between circuit power supply voltage Vcc and circuit ground. This trip point leads to improved noise margin.
The remainder of the circuit of FIG. 1a apart from the local reference sub-circuit 3 is constructed as follows. Bipolar transistors 12 and 14 with load resistors 13 and 15 respectively, form an emitter-coupled pair wherein the their emitters are connected to the collector of bipolar transistor 16. Bipolar transistor 16 has its base connected to the base of transistor 8 and the emitter of transistor 16 is connected to emitter resistor 17 which is connected to circuit ground. Bipolar transistors 18 and 20 with load resistors 19 and 21 respectively, form an emitter-coupled pair wherein the their emitters are connected to the collector of bipolar transistor 22. Bipolar transistor 22 forms an emitter coupled pair with bipolar transistor 24. The emitters of transistors 22 and 24 are connected to the collector of transistor 26. Transistor 24 has its collector connected to the collector of transistor 19. The emitter of transistor 26 is connected to emitter resistor 23 which is connected to circuit ground. The base of transistor 26 is connected to the bases of transistors 8 and 16. Bipolar transistor 28 has its base connected to the collector of transistor 21 and bipolar transistor 30 has its base connected to the collector of bipolar transistor 19. Circuit output OUT is taken from the emitter of transistor 28 and circuit output OUT is taken from the emitter of transistor 30. Bipolar transistor 32 is connected to the emitter of transistor 28 at its collector and bipolar transistor 32 is connected to the bases of transistors 8, 16, and 26 at its base. Bipolar transistor 34 is connected to transistor 30's emitter at its collector. The base of transistor 34 is connected to the base of transistor 32. The emitters of transistors 32 and 34 are connected to their emitter resistors, resistors 32 and 34, respectively. The base of transistor 12 serves as the input for input A while the base of transistor 14 serves as the input for input A. The base of transistor 22 serves as the input for input B while the base of transistor 24 serves as the input for input B.
In principal, the collector and emitter currents through transistor 8 are mirrored through n-type bipolar transistors 16, 26, 32 and 34. Transistors 12, 14 and 16 comprises a first current mirror. Transistors 18, 20, 22, 24 and 26 comprise a second current mirror. Transistors 28, 30, 32 and 34 comprise a third current mirror. For power down, ECL gates connected to local reference sub-circuit 3 can be turned off by turning off transistor 8. For instance, ECL bipolar transistor pairs comprising transistors 12 and 14, 18 and 20 and 22 and 24 are turned off when transistor 8 is shut off. Note that the remainder of the circuit in FIG. 1a comprises collector resistors 13, 15, 19 and 21 and emitter resistors 17, 23 25 and 27.
FIG. 1b illustrates a block diagram drawing of the local reference sub-circuit scheme wherein a local reference sub-circuit is connected to several current mirrors.
The logical function of the ECL circuit of FIG. 1a in response to inputs A and its complement A and B and its complement B is illustrated in Table A for an enabled circuit. Transistors are indicated by their corresponding numbers. Output OUT is taken from the collector of transistor 32 and the complement of output OUT, OUT, is taken from the collector of transistor 34. The on (ON) or off (OFF) states of each transistor shown in FIG. 1a is illustrated in table A. Note that "HI" refers to a logic high value for an input while "LO" refers to a logic low value for an input.
FIG. 1c illustrates transfer curves of the sum of currents through the circuit of FIG. 1a versus the voltage at enable input EN for the circuit of FIG. 1a. This current equals the current through resistors 7, 17, 23, 25 and 27 of FIG. 1a. A curve is drawn in FIG. 1c corresponding to the various nominal threshold voltages (the nominal threshold voltage value throughout herein is for example 0.5 volts and all threshold voltage values are expressed relative to a nominal threshold voltage value) of the n-channel transistors in the circuit of FIG. 1a, as labeled for each curve shown. For the graphs shown in FIG. 1c, circuit ground is considered as -3.3 volts and Vcc is considered as 0 volts. Note the sharp peaks (labeled a, b,
TABLE A __________________________________________________________________________ EN A A B B OUT OUT 2 4 6 8 10 12 14 __________________________________________________________________________ HI HI LO HI LO HI LO OFF ON ON OFF ON ON OFF HI LO HI HI LO HI LO OFF ON ON OFF ON OFF ON HI LO HI LO HI LO HI OFF ON ON OFF ON OFF ON HI HI LO LO HI HI LO OFF ON ON OFF ON ON OFF __________________________________________________________________________ 16 18 20 22 24 26 28 30 32 34 __________________________________________________________________________ ON OFF OFF OFF ON ON ON OFF ON ON ON OFF OFF OFF ON ON ON OFF ON ON ON OFF ON ON OFF ON OFF ON ON ON ON ON OFF ON OFF ON ON OFF ON ON __________________________________________________________________________
and c) in the wave characteristics. These sharp peaks occur during voltage transitions at enable input EN shown in FIG. 1a. These sharp peaks are due to crow bar current through inverters 9 and 11. Crow bar current is the transient leakage current which occurs simultaneously between source to drain through the p-channel and n-channel transistors of an inverter. The voltage change at the input of an inverter is not instantaneous and therefore there is a short period of time during the voltage transition at the gates of the inverter transistors (inverter input) in which both inverter transistors are turned on. Crow bar current through an inverter is undesirable, and the existence of crow bar current manifests itself in the sharp peaks shown in FIG. 1c. A low power standby mode is observed for the circuit of FIG. 1a by observing the low current and low voltage characteristics near zero milliamps for the graphs shown in FIG. 1c.
FIG. 1d illustrates transfer curves of load resistor voltage swing for a load resistor (13, 15, 19, or 21) of one of the emitter coupled pairs as a function of voltage at enable input EN for the circuit of FIG. 1a. Since substantially the same current is mirrored in the circuit of FIG. 1a, resistor 13, 15, 19 or 21 is representative of the load resistor. Each transfer curve is shown according to a nominal threshold voltage level for the n-channel transistors of FIG. 1a. For the graphs shown in FIG. 1c, Vcc is 0 volts and circuit ground is -3.3 volts. Noise margin indicates the amount of input voltage change tolerated before a change occurs at the output of a circuit. The voltage swing across a load resistor of one of the emitter coupled pairs is representative of the voltage change at the circuit output (OUT and OUT) distinguished by one base-emitter voltage drop since the same mirrored current value flows through the load resistors and since the load resistors are preferably of the same value. FIG. 1d indicates a noise margin of approximately -1.5 volts with respect to Vcc or 0 volts and a noise margin of 0.8 with respect to circuit ground or -3.3 volts. Although the current to voltage characteristic, as shown in FIG. 1c, of this circuit is poor, the noise margin is adequate. Hence, the circuit of FIG. 1a responds quickly (as demonstrated in FIG. 1d by the nearly vertical slope of the curves between 0 volts and -0.18 volts of the load resistor swing) to changes in the enable input voltage.